In a conventional semiconductor device (referred to as IC hereinafter) used in a tuner that includes a voltage-controlled oscillator circuit (referred to as VCO circuit hereinafter) and a phase-locked loop circuit (referred to as PLL circuit hereinafter), the VCO circuit and the PLL circuit continuously consume power.
Japanese Kokai Patent Application No. Hei 11 [1999]-127086 discloses technology pertaining to a common UHF and VHF tuner, which avoids complicated design and high manufacturing costs and has improved broadcast receiving performance by reducing the difference of receiving sensitivity as a function of the broadcasting frequency when receiving VHF band broadcasts. Japanese Kokai Patent Application No. 2005-130279 discloses technology pertaining to an inexpensive diversity receiving tuner that can constantly receive signals from an antenna with optimal reception.
FIG. 14 shows an example of the conventional IC and tuner. As shown in FIG. 14, a conventional IC6 comprises oscillation signal input terminal TVT14, oscillation signal output terminal TVO14, voltage control signal output terminals T1PL14 and T2PL14, reference oscillation signal terminals T1OS14 and T2OS14, received signal terminal TR14, antenna tuning circuit ANT14, radio-frequency amplifier circuit RFA14, intermediate-frequency amplifier circuit AMP14, intermediate-frequency signal terminal TIF14, VCO circuit VCO14, PLL circuit PLL14, and mixer M14.
Also, as shown in FIG. 14, tuner 5 comprises IC6, LC circuit LC14 including variable-capacitance diode VC14, low-pass filter LPF14, and crystal oscillator XTL14. The oscillation signal input terminal TVI14 and oscillation signal output terminal TVO14 of IC6 are connected to LC circuit LC14. The voltage control signal output terminals T1PL14 and T2PL14 are connected to low-pass filter LPF14. The reference oscillation signal terminals T1OS14 and T2OS14 are connected to crystal oscillator XTL14.
IC6 and tuner 5 operate as follows. The radio waves of a radio broadcast or a TV broadcast are received by an antenna outside of tuner 5. The received signal is input from received signal terminal TR14 to IC6. The received signal is tuned by antenna tuning circuit ANT14 in IC6 and amplified by radio-frequency amplifier circuit RFA14. Mixer M14 converts the frequency of the amplified received signal using the local oscillation signal OSC14 generated by VCO circuit VCO14 to generate an intermediate-frequency signal. After being amplification by intermediate-frequency amplifier circuit AMP14, the intermediate-frequency signal is output from intermediate-frequency signal terminal TIF14 of IC6 and transferred to a demodulator outside of tuner 5.
VCO circuit VCO14 generates local oscillation signal OSC14 together with LC circuit LC14 via oscillation signal input terminal TVI14 and oscillation signal output terminal TVO14. Crystal oscillator XTL14 and PLL circuit PLL14 generate a reference oscillation signal via reference oscillation signal terminals T1OS14 and T2OS14. PLL circuit PLL14 also compares the phase of the reference oscillation signal and local oscillation signal OSC14 to generate a voltage control signal with respect to VCO circuit VCO14. This signal is output from voltage control signal output terminals T1PL14 and T2PL14. The output voltage control signal is converted to a DC voltage by low-pass filter LPF14 to drive variable-capacitance diode VC14 in LC circuit LC14 to control the frequency of local oscillation signal OSC14 generated by VCO circuit VCO14.
FIG. 15 shows the configuration of VCO circuit VCO14 shown in FIG. 14 and the connection to LC circuit LC14. VCO circuit VCO14 comprises the first differential section DIF115 connected to oscillation signal input terminal TVI14 and oscillation signal output terminal TIVO14 and a second differential section DIF215 that outputs local oscillation signal OSC14. The first differential section DIF115 comprises capacitor C115, voltage source circuit V15, resistors R115-R415, differential input circuit DI115 comprising transistors TR115 and TR215 that are differentially connected, and constant current circuit I115. The second differential section DIF215 comprises resistors R515 and R615, differential input circuit DI215 comprising resistors TR315 and TR415 that are differentially connected, and constant current circuit I215. Oscillation signal input terminal TVI14 and oscillation signal output terminal TVO14 are connected to LC circuit LC14 outside the IC as shown in FIG. 15.
VCO circuit VCO14 operates as follows. The first differential section DIF115 constitutes an oscillator along with LC circuit LC14. The feedback oscillation signal of LC circuit LC14 input from oscillation signal input terminal TVI14 is amplified by the first differential section DIF115 and is output from oscillation signal output terminal TV1O14.
The second differential section DIF215 constitutes a buffer circuit. The feedback oscillation signal input to the base of transistor TR215 of the first differential section DIF115 is also input as a differential input to the differential input circuit DI215 of the second differential section DIF215. The second differential section DIF215 converts the input feedback oscillation signal into a current mode signal and outputs it as local oscillation signal OSC14 to mixer M14. Local oscillation signal OSC14 is output as a differential signal from VCO circuit VCO14 to mixer M14.
In this case, the constant current circuit I115 in the first differential section DIF115 and the constant current circuit I215 in the second differential section DIF215 are in continuous operation. Thus, current flows continuously in the path from the power lines of the first differential section DIF115 and the second differential section DIF215 to ground. Therefore, VCO circuit VCO14 continuously consumes power.
FIG. 16 shows the configuration of PLL circuit PLL14 shown in FIG. 14. As shown in this figure, PLL circuit PLL14 comprises local oscillation signal frequency dividing circuit DIV116, reference oscillator circuit XOS16, reference oscillation signal frequency dividing circuit DIV216, phase detecting circuit CMP16, and charge pump circuit CP16. These circuits receive power supplied from power line VDD16 shared by mixer M14 and other circuits of an IC.
PLL circuit PLL14 operates as follows. Reference oscillator circuit XOS16 receives the oscillation signal from crystal oscillator XTL14 via reference oscillation signal terminals T1OS14 and T2OS14 and generates a reference oscillation signal. The frequency of the reference oscillation signal is divided by reference oscillation signal frequency dividing circuit DIV216, and the signal is then input to phase detecting circuit CMP16. The frequency of local oscillation signal OSC14 generated by VCO circuit VCO14 is divided by local oscillation signal frequency dividing circuit DIV116, and the signal is then input to phase detecting circuit CMP16. Phase detecting circuit CMP16 compares the phase of the two frequency-divided oscillation signals and outputs a phase detecting signal. Charge pump circuit CP16 generates a voltage control signal corresponding to the phase difference from the phase detecting signal. The voltage control signal is output to voltage control signal output terminals T1PL14 and T2PL14.
Power is continuously supplied to the power line VDD16 of local oscillation signal frequency dividing circuit DIV116, reference oscillator circuit XOS16, reference oscillation signal frequency dividing circuit DIV216, phase detecting circuit CMP16, and charge pump circuit CP16. Consequently, these circuits continuously consume power.
The configuration using two IC6 is well known in conventional diversity receivers. In this type of diversity receiver, local oscillation signals having the same frequency are generated by the VCO circuit and PLL circuit of the respective IC6.
FIG. 17 shows a conventional diversity receiver constituted using two IC6. As shown in this figure, diversity receiver 300 comprises antennas A117 and A217, two tuners 5 (5117 and 5217), demodulators DM117 and DM217, and comparator DCM17 that selects one of the two demodulated signals.
Also, as shown in FIG. 17, each tuner 5 has one IC6 (6117 or 6217), LC circuit LC14 including a variable-capacitance diode VC14, one low-pass filter LPF14, and one crystal oscillator XTL14.
Diversity receiver 300 operates as follows. Antennas A117 and A217 receive the same broadcast signal. IC6117 converts the frequency of the signal received from antenna A117. In other words, the signal received by antenna A117 is input to IC6117 at received signal terminal TR14. After being tuned by antenna tuning circuit ANT14 and amplified by radio-frequency amplifier circuit RFA14, the received signal is input to mixer M14. The VCO circuit VCO14 and PLL circuit PLL14 of IC6117 and the LC circuit LC14 of tuner 5117 generate local oscillation signal OSC117. Mixer M14 converts the frequency of the received signal using local oscillation signal OSC117 to generate an intermediate-frequency signal. The intermediate-frequency signal is amplified by intermediate-frequency amplifier circuit AMP14, output from intermediate-frequency signal terminal TIF14 of IC6117, and input to demodulator DM117. The demodulated signal generated by demodulator DM117 is input to comparator DCM17.
IC6217 converts the frequency of the signal received from antenna A217 in the same way. The demodulated signal generated by demodulator DM217 is input to comparator DCM17.
Since the receiving conditions vary as a function of the orientation of the antennas, there is qualitative difference between the demodulated signal generated by demodulator DM117 from the signal received from antenna A117 and the demodulated signal generated by demodulator DM217 from the signal received from antenna A217. Comparator DCM17 compares the two demodulated signals and selects the demodulated signal obtained from the received signal with the better reception state and outputs that signal from the diversity receiver.
In this case, local oscillation signals OSC117 and OSC217 having the same frequency are generated by the VCO circuit and PLL circuit of the respective IC6 and are used in frequency conversion of the received signal. There is another configuration of diversity receiver using two types of ICs, that is, IC6 and a mixer unit IC having no VCO circuit or PLL circuit.
FIG. 18 shows the diversity receiver constituted by using two types of ICs. As shown in FIG. 18, diversity receiver 400 comprises antennas A118 and A218, tuner 5118 using IC6, mixer unit IC518, demodulators DM118 and DM218, and mixer DCM18 that selects one of two demodulated signals.
Tuner 5118 comprises one IC6 6118, LC circuit LC14 including a variable-capacitance diode VC14, one low-pass filter LPF14, and one crystal oscillator XTL14.
As shown in FIG. 18, mixer unit IC518 comprises received signal terminal TR18, antenna tuning circuit ANT18, radio-frequency amplifier circuit RFA18, intermediate-frequency amplifier circuit AMP18, intermediate-frequency signal terminal TIF18, and mixer M18. It has no VCO circuit or PLL circuit.
Diversity receiver 400 operates as follows. Antennas A118 and A218 receive the same broadcast signal. IC6118 converts the frequency of the signal received from antenna A118. The signal received by antenna A118 is input to IC6118 at received signal terminal TR14. After being tuned by antenna tuning circuit ANT14 and amplified by radio-frequency amplifier circuit RFA14, the received signal is input to mixer M14. The VCO circuit VCO14 of IC6118 and LC circuit LC14 generate local oscillation signal OSC14. Mixer M14 converts the frequency of the received signal using the local oscillation signal OSC14 to generate an intermediate-frequency signal. The intermediate-frequency signal is amplified by intermediate-frequency amplifier circuit AMP14, output from intermediate-frequency signal terminal TIF14 of IC6118, and input to demodulator DM118. The demodulated signal generated by demodulator DM118 is input to comparator DCM18.
On the other hand, mixer unit IC518 converts the frequency of the signal received from antenna A218. The signal received by antenna A218 is input to mixer unit IC518 from received signal terminal TR18. After being tuned by antenna tuning circuit ANT18 and amplified by radio-frequency amplifier circuit RFA18, the received signal is input to mixer M18. However, since mixer unit IC518 has no VCO circuit or PLL circuit, the local oscillation signal OSC14 generated by IC6118 is supplied to mixer unit IC518 and is used in the frequency conversion performed in mixer M18. The intermediate-frequency signal obtained after the frequency conversion is amplified by intermediate-frequency amplifier circuit AMP18, output from the intermediate-frequency signal terminal TIF18 of IC518, and input to demodulator DM218. The demodulated signal generated by demodulator DM218 is input to comparator DCM18.
Like the comparator DCM17 of diversity receiver 300, the comparator DCM18 of diversity receiver 400 compares the two demodulated signals, selects the demodulated signal obtained from the received signal with the better reception state, and outputs that demodulated signal from the diversity receiver.
However, in the conventional diversity receiver shown in FIG. 17 using two IC6, whereas it would suffice if local oscillation signal were generated by one circuit, here it is generated by the VCO circuit and PLL circuit of each IC6. As a result, unnecessary power is consumed.
Also, in the diversity receiver constituted using two types of ICs as shown in FIG. 18, since the circuit pattern and IC size of IC6 and mixer unit IC518 differ, the operating characteristics of the IC also differ, making it difficult to maintain uniform operating characteristics. Also, each time there is change in semiconductor processing technology, IC6 and mixer unit IC518 must be redesigned separately, leading to an increase in development costs.
A general object of the present invention is to provide a technology that can reduce unnecessary power consumption, improve the uniformity of the operating characteristics, and reduce the development costs of the IC and the diversity receiver constituted by a plurality of said ICs.